The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a static random access memory bitcell and methods for forming a static random access memory bitcell.
Static random access memory (SRAM) may be used, for example, to temporarily store data in a computer system. When continuously powered, the memory state of an SRAM persists without the need for data refresh operations. An SRAM device includes an array of bitcells in which each bitcell retains a single bit of data during operation. Each SRAM bitcell may include a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select the SRAM cell for read or write operations. A two-port SRAM is implemented by adding a read port that includes an additional pair of transistors. The addition of the transistor pair allows multiple read or write operations to occur concurrently or almost concurrently.
Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow in a channel region arranged between the source and drain. The channel region of a planar field-effect transistor is located beneath the top surface of a substrate on which the gate electrode is supported. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region to produce a device output current.
Planar field-effect transistors and fin-type field-effect transistors constitute a general category of field-effect transistor structures in which the direction of gated current in the channel region is in a horizontal direction parallel to the substrate surface. A vertical-transport field-effect transistor is a type of non-planar field-effect transistor in which the source and the drain are respectively arranged at the top and bottom of a semiconductor fin. The channel region of a vertical-transport field-effect transistor is arranged in the semiconductor fin between the source and the drain. The direction of gated current in the channel region of a vertical-transport field-effect transistor is in a vertical direction relative to the substrate surface and, therefore, in a direction that is parallel to the height of the semiconductor fin.